Currently, a read-modify-write process for a memory device requires two cycles, one to read and the other to write. This is required because many of the memory devices do not have an output enable which would permit the read-modify-write operation to occur in one cycle.
For example, a 36-bit memory device would be comprised of 8 X4 DRAMs (dynamic random access memories) and 4 X1 DRAMs. The X4 DRAMs are used to store the data and the X1 DRAMs are used to store the parity or the error correction data. Because the Xl DRAMs do not have output enable lines, a read-modify-write must be conducted as separate read and write functions.